VHDL-Based Implementation of NTT on FPGA
Result description
This paper is focused on the effective hardware-accelerated implementation of NTT (Number Theoretic Transform) and inverse NTT (NTT−1) on FPGA (Field Programmable Gate Array). The discussed implementation is intended for the use in the lattice-based cryptography schemes, e.g. CRYSTALS-Dilithium digital signature scheme which is one of the finalists of the third round in the post-quantum standardization process under the auspices of NIST (The National Institute of Standards and Technology). The implementation of NTT (NTT−1) requires 1798 (2547) Look-Up Tables (LUTs), 2532 (3889) Flip-Flops (FFs) and 48 (84) Digital Signal Processing blocks (DSPs). The latency of the design is 502 (517) clock cycles at the frequency 637 MHz on Xilinx Virtex UltraScale+ architecture which makes the presented implementation to be currently the fastest one. Regarding the inverse NTT, this is the first implementation at all.
Keywords
The result's identifiers
Result code in IS VaVaI
Result on the web
https://www.fekt.vut.cz/conf/EEICT/archiv/sborniky/EEICT_2021_sbornik_2.pdf
DOI - Digital Object Identifier
—
Alternative languages
Result language
angličtina
Original language name
VHDL-Based Implementation of NTT on FPGA
Original language description
This paper is focused on the effective hardware-accelerated implementation of NTT (Number Theoretic Transform) and inverse NTT (NTT−1) on FPGA (Field Programmable Gate Array). The discussed implementation is intended for the use in the lattice-based cryptography schemes, e.g. CRYSTALS-Dilithium digital signature scheme which is one of the finalists of the third round in the post-quantum standardization process under the auspices of NIST (The National Institute of Standards and Technology). The implementation of NTT (NTT−1) requires 1798 (2547) Look-Up Tables (LUTs), 2532 (3889) Flip-Flops (FFs) and 48 (84) Digital Signal Processing blocks (DSPs). The latency of the design is 502 (517) clock cycles at the frequency 637 MHz on Xilinx Virtex UltraScale+ architecture which makes the presented implementation to be currently the fastest one. Regarding the inverse NTT, this is the first implementation at all.
Czech name
—
Czech description
—
Classification
Type
D - Article in proceedings
CEP classification
—
OECD FORD branch
20206 - Computer hardware and architecture
Result continuities
Project
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
S - Specificky vyzkum na vysokych skolach
Others
Publication year
2021
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings II of the 27th Conference STUDENT EEICT 2021
ISBN
978-80-214-5943-4
ISSN
—
e-ISSN
—
Number of pages
5
Pages from-to
136-140
Publisher name
Neuveden
Place of publication
Vysoké učení technické v Brně, Fakulta elektrote
Event location
Brno
Event date
Apr 27, 2021
Type of event by nationality
CST - Celostátní akce
UT code for WoS article
—
Basic information
Result type
D - Article in proceedings
OECD FORD
Computer hardware and architecture
Year of implementation
2021