Implementation of a Multipath Fully Differential OTA in 0.18-mu m CMOS Process

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F22%3APU146817" target="_blank" >RIV/00216305:26220/22:PU146817 - isvavai.cz</a>
Alternative codes found
RIV/68407700:21460/23:00362546
Result on the web
<a href="https://ieeexplore.ieee.org/document/9944072" target="_blank" >https://ieeexplore.ieee.org/document/9944072</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/TVLSI.2022.3218741" target="_blank" >10.1109/TVLSI.2022.3218741</a>

Result language
angličtina
Original language name
Implementation of a Multipath Fully Differential OTA in 0.18-mu m CMOS Process
Original language description
This brief implements a highly efficient fully differential transconductance amplifier, based on several input-to-output paths. Some traditional techniques, such as positive feedback, nonlinear tail current sources, and current mirror-based paths, are combined to increase the transconductance, thus leading to larger dc gain and higher gain bandwidth (GBW) product. Two flipped voltage-follower (FVF) cells are employed as variable current sources to provide class-AB operation and adaptive biasing of all other drivers. The proposed structure includes several input-to-output paths that play the role of dynamic current boosters during the slewing phase, thus improving the slew rate (SR) performance. The circuit was fabricated in a TSMC 0.18-mu m CMOS process with a silicon area of 54.5 x 30.1 mu m. Experimental results show a GBW of 173.3 MHz, a dc gain of 72.7 dB, and an SR of 139.4 V/mu s for a capacitive load of 2 x 5 pF. The proposed circuit consumes 619 mu W of power, under a supply voltage of 1.8 V.
Czech name
—
Czech description
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Type
J<sub>imp</sub> - Article in a specialist periodical, which is included in the Web of Science database
CEP classification
—
OECD FORD branch
20200 - Electrical engineering, Electronic engineering, Information engineering

Publication year
2022
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Name of the periodical
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
ISSN
1063-8210
e-ISSN
1557-9999
Volume of the periodical
31
Issue of the periodical within the volume
1
Country of publishing house
US - UNITED STATES
Number of pages
5
Pages from-to
147-151
UT code for WoS article
000881953100001
EID of the result in the Scopus database
2-s2.0-85141614955

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