A Rail-to-Rail Transconductance Amplifier Based on Current Generator Circuits

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F60162694%3AG43__%2F24%3A00560573" target="_blank" >RIV/60162694:G43__/24:00560573 - isvavai.cz</a>
Alternative codes found
RIV/68407700:21460/23:00368948 RIV/00216305:26220/23:PU149231
Result on the web
<a href="https://doi.org/10.1109/TVLSI.2023.3285823" target="_blank" >https://doi.org/10.1109/TVLSI.2023.3285823</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/TVLSI.2023.3285823" target="_blank" >10.1109/TVLSI.2023.3285823</a>

Result language
angličtina
Original language name
A Rail-to-Rail Transconductance Amplifier Based on Current Generator Circuits
Original language description
In this brief, two current generator circuits are used to design a self-biasing transconductance amplifier. The current generators are configured using two n-channel and p-channel cascode current mirrors by which a high input dynamic range is achieved. Since such a topology creates positive feedback, the transconductance of the circuit is also increased causing higher performance. To ensure the stability of the circuit, constant current sources can be paralleled with the current mirror topologies, which of course are implemented using input drivers. Therefore, two n-channel and p-channel input differential pairs are added to the current generator circuits by which not only a rail-to-rail operation is achieved but also the amplifier is stabilized. The proposed circuit was fabricated in the TSMC 0.18-mu m CMOS process with a silicon area of 54.1 x 71 mu m. Under a 1.8-V supply voltage, the experimental results showed a high input common-mode range (ICMR), while a gain bandwidth (GBW) of 83.9 MHz was measured for a capacitive load of 2 x 6 pF. In addition, a dc gain and a slew rate (SR) of 68.4 dB and 71.7 V/mu s, respectively, were achieved.
Czech name
—
Czech description
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Type
J<sub>imp</sub> - Article in a specialist periodical, which is included in the Web of Science database
CEP classification
—
OECD FORD branch
20206 - Computer hardware and architecture

Publication year
2023
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Name of the periodical
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
ISSN
1063-8210
e-ISSN
1557-9999
Volume of the periodical
31
Issue of the periodical within the volume
10
Country of publishing house
US - UNITED STATES
Number of pages
5
Pages from-to
1624-1628
UT code for WoS article
001079713600014
EID of the result in the Scopus database
2-s2.0-85163556138

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