FET Gate Driver Utilising Transient Gate Overvoltage
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F23%3APU148858" target="_blank" >RIV/00216305:26220/23:PU148858 - isvavai.cz</a>
Result on the web
<a href="https://ieeexplore.ieee.org/document/10168351" target="_blank" >https://ieeexplore.ieee.org/document/10168351</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/ISSE57496.2023.10168351" target="_blank" >10.1109/ISSE57496.2023.10168351</a>
Alternative languages
Result language
angličtina
Original language name
FET Gate Driver Utilising Transient Gate Overvoltage
Original language description
In this paper a method for driving field effect transistors is described. This method uses a short high-voltage pulse on the gate to mitigate the effects of parasitic gate inductance and resistance. The proposed driver was able to reduce the fall time of drain voltage from 12 ns to 4 ns compared to conventional driving.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
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OECD FORD branch
20201 - Electrical and electronic engineering
Result continuities
Project
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Continuities
S - Specificky vyzkum na vysokych skolach
Others
Publication year
2023
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
2023 46th International Spring Seminar on Electronics Technology (ISSE)
ISBN
979-8-3503-3484-5
ISSN
2161-2536
e-ISSN
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Number of pages
5
Pages from-to
1-5
Publisher name
IEEE
Place of publication
neuveden
Event location
Timisoara
Event date
May 10, 2023
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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