Hardware Implementation of ASCON
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F23%3APU149090" target="_blank" >RIV/00216305:26220/23:PU149090 - isvavai.cz</a>
Result on the web
<a href="https://csrc.nist.gov/events/2023/lightweight-cryptography-workshop-2023" target="_blank" >https://csrc.nist.gov/events/2023/lightweight-cryptography-workshop-2023</a>
DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Hardware Implementation of ASCON
Original language description
In this work, we present various hardware implementation for ASCON. We cover encryption + tag generation as well as decryption + tag verification for ASCON AEAD and also ASCON hash function. On top the usual (unprotected) implementation, we present side channel protection (threshold countermeasure) and triplication/majority based fault protection. The side channel and fault protections work orthogonal to each other (i.e., either one can be turned on/off without affecting the other). We also show ASIC and FPGA benchmarks for our implementations.
Czech name
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Czech description
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Classification
Type
O - Miscellaneous
CEP classification
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OECD FORD branch
20202 - Communication engineering and systems
Result continuities
Project
<a href="/en/project/VJ02010010" target="_blank" >VJ02010010: Tools for AI-enhanced Security Verification of Cryptographic Devices</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2023
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů