High-speed Side-channel-protected Encryption and Authentication in Hardware

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F18%3A00342759" target="_blank" >RIV/68407700:21240/18:00342759 - isvavai.cz</a>
Result on the web
<a href="https://eprint.iacr.org/2018/1088.pdf" target="_blank" >https://eprint.iacr.org/2018/1088.pdf</a>
DOI - Digital Object Identifier
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Result language
angličtina
Original language name
High-speed Side-channel-protected Encryption and Authentication in Hardware
Original language description
This paper describes two FPGA implementations for the encryption andauthentication of data, based on the AES algorithm running in Galois/Counter mode(AES-GCM). Both architectures are protected against side-channel analysis attacks through the use of a threshold implementation (TI). The first architecture is fully unrolled and optimized for throughput. The second architecture uses a round-based structure, fits on a relatively small FPGA board, and is evaluated for side-channel attack resistance. We perform a Test Vector Leakage Assessment (TVLA), which shows no first-order leakage in the power consumption of the FPGA. To the best of our knowledge, our work is (1) the first to describe a throughput-optimized FPGA architecture of AES-GCM, protected against first-order side-channel information leakage, and (2) the first to evaluate the side-channel attack resistance of a TI-protected AES-GCM implementation.
Czech name
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Czech description
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Project
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Continuities
I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace

Publication year
2018
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

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