Dynamic Logic Reconfiguration Based Side-Channel Protection of AES and Serpent
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F19%3A00333735" target="_blank" >RIV/68407700:21240/19:00333735 - isvavai.cz</a>
Result on the web
<a href="http://dx.doi.org/10.1109/DSD.2019.00048" target="_blank" >http://dx.doi.org/10.1109/DSD.2019.00048</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/DSD.2019.00048" target="_blank" >10.1109/DSD.2019.00048</a>
Alternative languages
Result language
angličtina
Original language name
Dynamic Logic Reconfiguration Based Side-Channel Protection of AES and Serpent
Original language description
Dynamic logic reconfiguration is a concept which allows for efficient on-the-fly modifications of combinational circuit behaviour in both ASIC and FPGA devices. The reconfiguration of Boolean functions is achieved by modification of their generators (e.g. shift register-based look-up tables) and it can be controlled from within the chip, without the necessity of any external intervention. This hardware polymorphism can be utilized for the implementation of side-channel attack countermeasures, as demonstrated by Sasdrich et al. for the lightweight cipher PRESENT. In this work we adopt these countermeasures to two of the AES finalists, namely Rijndael and Serpent. Just like PRESENT, both Rijndael and Serpent are block ciphers based on a substitution-permutation network. We describe the countermeasures and adjustments necessary to protect these ciphers using the resources available in modern Xilinx FPGAs. We describe our VHDL implementations and evaluate the side-channel leakage and effectiveness of different countermeasure combinations using a methodology based on Welch’s t-test. We did not detect any significant leakage from the fully protected versions of our implementations. We show that the countermeasures proposed by Sasdrich et al. are, with some modifications compared to the protected PRESENT implementation, successfully applicable to AES and Serpent.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
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OECD FORD branch
20206 - Computer hardware and architecture
Result continuities
Project
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Continuities
S - Specificky vyzkum na vysokych skolach
Others
Publication year
2019
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of the 22nd Euromicro Conference on Digital Systems Design
ISBN
978-1-7281-2861-0
ISSN
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e-ISSN
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Number of pages
6
Pages from-to
277-282
Publisher name
IEEE Computer Soc.
Place of publication
Los Alamitos, CA
Event location
Kallithea, Chalkidiki
Event date
Aug 28, 2019
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000722275400039