High-level synthesis, cryptography, and side-channel countermeasures: A comprehensive evaluation

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F21%3A00350674" target="_blank" >RIV/68407700:21240/21:00350674 - isvavai.cz</a>

Result on the web

<a href="https://doi.org/10.1016/j.micpro.2021.104311" target="_blank" >https://doi.org/10.1016/j.micpro.2021.104311</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1016/j.micpro.2021.104311" target="_blank" >10.1016/j.micpro.2021.104311</a>

Result language

angličtina

Original language name

High-level synthesis, cryptography, and side-channel countermeasures: A comprehensive evaluation

Original language description

Side-channel attacks pose a severe threat to both software and hardware cryptographic implementations. Current literature presents various countermeasures against these kinds of attacks, based on approaches such as hiding or masking, implemented either in software, or on register-transfer level or gate level in hardware. However, emerging trends in hardware design lean towards a system-level approach, allowing for faster, less error-prone, design process, an efficient hardware/software co-design, or sophisticated validation, verification, and (co)simulation strategies. In this paper, we propose a Boolean masking scheme suitable for high-level synthesis of substitution-permutation network-based encryption. We implement both unprotected and protected PRESENT, AES/Rijndael and Serpent encryption in C language, utilizing the concept of dynamic logic reconfiguration, synthesize it for Xilinx FPGA, and we compare our results regarding time and area utilization. We evaluate the effectiveness of proposed countermeasures using both specific and non-specific t-test leakage assessment methodology. We discuss the leakage assessment results, and we identify and discuss the related limitations of the system-level approach and the high-level synthesis.

Czech name

—

Czech description

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Type

J_imp - Article in a specialist periodical, which is included in the Web of Science database

CEP classification

—

OECD FORD branch

20206 - Computer hardware and architecture

Project

—

Continuities

S - Specificky vyzkum na vysokych skolach

Publication year

2021

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Name of the periodical

Microprocessors and Microsystems

ISSN

0141-9331

e-ISSN

1872-9436

Volume of the periodical

85

Issue of the periodical within the volume

104311

Country of publishing house

NL - THE KINGDOM OF THE NETHERLANDS

Number of pages

13

Pages from-to

1-13

UT code for WoS article

000689666100006

EID of the result in the Scopus database

2-s2.0-85111677981