Towards High-Level Synthesis of Polymorphic Side-Channel Countermeasures

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F20%3A00342201" target="_blank" >RIV/68407700:21240/20:00342201 - isvavai.cz</a>
Result on the web
<a href="https://doi.org/10.1109/DSD51259.2020.00040" target="_blank" >https://doi.org/10.1109/DSD51259.2020.00040</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/DSD51259.2020.00040" target="_blank" >10.1109/DSD51259.2020.00040</a>

Result language
angličtina
Original language name
Towards High-Level Synthesis of Polymorphic Side-Channel Countermeasures
Original language description
Side-channel attacks pose a severe threat to both software and hardware cryptographic implementations. Current literature presents various countermeasures against these kinds of attacks, based on approaches such as hiding or masking, implemented either in software, or on register-transfer or gate-level in hardware. However, emerging trends in hardware design lean towards a system-level approach, allowing for faster, less error-prone, design process, an efficient hardware/software co-design, or sophisticated validation, verification, and (co)simulation strategies. In this paper, we propose a Boolean masking scheme suitable for high-level synthesis. We implement a protected PRESENT encryption in C language, utilizing the concept of dynamic logic reconfiguration, synthesize it for Xilinx Artix 7 FPGA, and we compare our results regarding clock cycle latency and area utilization. We evaluate the effectiveness of proposed countermeasures using specific t-test leakage assessment methodology. We show that our high-level synthesis implementation successfully conceals the side-channel leakage while maintaining reasonable area and latency overhead.
Czech name
—
Czech description
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Publication year
2020
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of the 23rd Euromicro Conference on Digital Systems Design
ISBN
978-1-7281-9535-3
ISSN
—
e-ISSN
—
Number of pages
7
Pages from-to
193-199
Publisher name
IEEE Computer Soc.
Place of publication
Los Alamitos, CA
Event location
Virtual Event organized from Kranj, Slovenia
Event date
Aug 26, 2020
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000630443300029

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