Fractional-Order Immitance Converter (FGIC44) Performance Using Wideband Fractional-Order Element Seeds

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F24%3APU151912" target="_blank" >RIV/00216305:26220/24:PU151912 - isvavai.cz</a>
Result on the web
<a href="http://dx.doi.org/10.1109/SOUTHEASTCON52093.2024.10500206" target="_blank" >http://dx.doi.org/10.1109/SOUTHEASTCON52093.2024.10500206</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/SOUTHEASTCON52093.2024.10500206" target="_blank" >10.1109/SOUTHEASTCON52093.2024.10500206</a>

Result language
angličtina
Original language name
Fractional-Order Immitance Converter (FGIC44) Performance Using Wideband Fractional-Order Element Seeds
Original language description
One method to approximate and realize a fractional order impedance uses RC-ladder circuits to realize the target phase and magnitude characteristics over a desired frequency band. This method when paired with a controllable immitance converter (FGIC44) can realize a range of fractional-orders using one to two seeds and not require a complete ladder redesign. In this work, the performance of the FGIC44 using two approximated fractional-order seeds (with < 2 degrees phase error from 40 Hz to 1 MHz) is shown to realize fractional orders of alpha = +/- 0.205, 0.615, 0.820, and 1.025. While accurate performance of the design was limited to the frequency band from 40 Hz to 10 kHz, this pilot does validate using two fractional order seeds with the FGIC44.
Czech name
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Czech description
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Project
<a href="/en/project/GA23-06070S" target="_blank" >GA23-06070S: Fundamental research on designing of CMOS fractional-order elements</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year
2024
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

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