Design, synthesis and simulation of fractional-order element using MOS transistors as distributed resistive capacitive devices

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F26%3A0197765" target="_blank" >RIV/00216305:26220/26:0197765 - isvavai.cz</a>

Result on the web

<a href="https://link.springer.com/article/10.1038/s41598-025-96539-w" target="_blank" >https://link.springer.com/article/10.1038/s41598-025-96539-w</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1038/s41598-025-96539-w" target="_blank" >10.1038/s41598-025-96539-w</a>

Result language

angličtina

Original language name

Design, synthesis and simulation of fractional-order element using MOS transistors as distributed resistive capacitive devices

Original language description

The article presents a synthesis method to design electrical circuit elements with fractional-order impedance, referred to as a Fractional-Order Element (FOE) or Fractor, that can be implemented by Metal-Oxide-Semiconductor (MOS) transistors. This provides an approach to realize this class of device using current integrated circuit manufacturing technologies. For this synthesis MOS transistors are treated as uniform distributed resistive-capacitive layer structures. The synthesis approach adopts a genetic algorithm to generate the MOS structures interconnections and dimensions to realize an FOE with user-defined constant input admittance phase, allowed ripple deviations, and target frequency range. A graphical user interface for the synthesis process is presented to support its wider adoption. We synthetized and present FOEs with admittance phase from 5 degrees to 85 degrees. The design approach is validated using Cadence post-layout simulations of an FOE design with admittance phase of 74 +/- 1 degrees realized using native n-channel MOS devices in TSMC 65 nm technology. Overall, the post-layout simulations demonstrate magnitude and phase errors less than 0.5% and 0.1 degrees, respectively, compared to the synthesis expected values in the frequency band from 1 kHz to 10 MHz. This supports that the design approach is appropriate for the future fabrication and validation of FOEs using this process technology.

Czech name

—

Czech description

—

Type

J_imp - Article in a specialist periodical, which is included in the Web of Science database

CEP classification

—

OECD FORD branch

20201 - Electrical and electronic engineering

Project

<a href="/en/project/GA23-06070S" target="_blank" >GA23-06070S: Fundamental research on designing of CMOS fractional-order elements</a><br>

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year

2025

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Name of the periodical

Scientific Reports

ISSN

2045-2322

e-ISSN

—

Volume of the periodical

15

Issue of the periodical within the volume

4

Country of publishing house

GB - UNITED KINGDOM

Number of pages

18

Pages from-to

—

UT code for WoS article

001478305300004

EID of the result in the Scopus database

2-s2.0-105003691263