Partial Scan Methodology in VHDL Environment

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F99%3A43801065" target="_blank" >RIV/00216305:26220/99:43801065 - isvavai.cz</a>

Result on the web

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DOI - Digital Object Identifier

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Result language

angličtina

Original language name

Partial Scan Methodology in VHDL Environment

Original language description

The paper presents a partial scan design methodology suited for pipelined data paths described at the Register Transfer Level. The presented methodology can be used for the selection of registers into the partial scan chain.

Czech name

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Czech description

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Type

D - Article in proceedings

CEP classification

JC - Computer hardware and software

OECD FORD branch

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Project

<a href="/en/project/GA102%2F98%2F1463" target="_blank" >GA102/98/1463: Methodology and tools for digital circuits testability analysis</a><br>

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year

1999

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

CEI'99

ISBN

80-88922-05-4

ISSN

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e-ISSN

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Number of pages

6

Pages from-to

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Publisher name

TU Košice

Place of publication

Herľany, SR

Event location

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Event date

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Type of event by nationality

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UT code for WoS article

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