Performance Prediction Model of Bus-Based Shared Memory Architectures

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F02%3APU36198" target="_blank" >RIV/00216305:26230/02:PU36198 - isvavai.cz</a>
Result on the web
—
DOI - Digital Object Identifier
—

Result language
angličtina
Original language name
Performance Prediction Model of Bus-Based Shared Memory Architectures
Original language description
It is shown that cache-coherent bus-based multiprocessor simulation can be implemented using message passing and few shared variables, at least in the case of an atomic bus and known coherence protocols. Data request and write-back bus transactions are generating messages to a shared memory server process, shared variables are used only for synchronization. A change in their values by one process is visible simultaneously to other processes, where it triggers invalidation/update actions. Models of variious locks and barriers are described and the simulation-based performance prediction using Transim tool is illustrated on the example of parallel FFT benchmark in OpenMP. Multiprocessor hw, sw, and mapping to one another is described in Transim languagethat supports synchronous message passing as well as shared variables. Accuracy of prediction (8 %) has been satisfactory in the benchmark under test and may continue to be so in other benchmarks.
Czech name
—
Czech description
—

Publication year
2002
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of 36th International Conference MOSIS'02 Modelling and Simulation of Systems
ISBN
80-85988-71-2
ISSN
—
e-ISSN
—
Number of pages
8
Pages from-to
273-280
Publisher name
Neuveden
Place of publication
Ostrava
Event location
Rožnov pod Radhoštěm
Event date
Apr 22, 2002
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
—

Similar results(10)