A Multi-protocol cache controller

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F03%3APU42500" target="_blank" >RIV/00216305:26230/03:PU42500 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
A Multi-protocol cache controller
Original language description
Bus-based shared memory multiprocessors with per-processor caches use either invalidation or update protocols to maintain cache coherence. This paper suggests mixing protocols for different data objects within a single application, depending on whateverprotocol is more efficient for an access pattern to a given object. The model of a two-protocol cache coherence controller has been created in CSP-based Transim language. Each cache line is tagged not only with the state, but also with the protocol typee. Two most frequent 4-state, write-back protocols are implemented: MESI (invalidation) and Dragon (update) protocol. The model will be used for experimental evaluation of the proposed controller, which could then be used for processor cores with primarycaches in SoC or for secondary caches in multiprocessors with standard microprocessors.
Czech name
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Czech description
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Project
<a href="/en/project/GA102%2F02%2F0503" target="_blank" >GA102/02/0503: Parallel performance prediction and tuning</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year
2003
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
IFAC Workshop on Programmable devices and systems - PDS 2003
ISBN
0-08-044130-0
ISSN
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e-ISSN
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Number of pages
6
Pages from-to
220-225
Publisher name
VŠB - Technical University of Ostrava
Place of publication
Ostrava
Event location
Ostrava
Event date
Feb 11, 2003
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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