Test Controller Design Based on VHDL Source File Analysis
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F02%3APU36255" target="_blank" >RIV/00216305:26230/02:PU36255 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Test Controller Design Based on VHDL Source File Analysis
Original language description
In the paper the process of test controller design and synthesis on register transfer level (RTL) is described. The sequence of control, address and data signals together with circuit structure for which the test controller is designed are the input information of the problem. The methodology of transforming an RTL circuit into a labelled directed graph and then into VHDL source code will be presented. The ideas of test controller synthesis based on this information will be explicitly shown.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
<a href="/en/project/GA102%2F01%2F1531" target="_blank" >GA102/01/1531: Formal approaches in digital circuit diagnostics - testable design verification</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2002
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of The Fifth International Scientific Conference Electronic Computers and Informatics 2002
ISBN
80-7099-879-2
ISSN
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e-ISSN
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Number of pages
6
Pages from-to
135-140
Publisher name
Neuveden
Place of publication
Letná 42, 040 01 TU Košice
Event location
Kosice-Herlany
Event date
Oct 10, 2002
Type of event by nationality
EUR - Evropská akce
UT code for WoS article
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