Efficient Implementation of Bi-functional RTL Components - Case Study
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F18%3APU130787" target="_blank" >RIV/00216305:26230/18:PU130787 - isvavai.cz</a>
Result on the web
<a href="http://dx.doi.org/10.1109/NGCAS.2018.8572235" target="_blank" >http://dx.doi.org/10.1109/NGCAS.2018.8572235</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/NGCAS.2018.8572235" target="_blank" >10.1109/NGCAS.2018.8572235</a>
Alternative languages
Result language
angličtina
Original language name
Efficient Implementation of Bi-functional RTL Components - Case Study
Original language description
The emergence of highly optimized implementations of many bi-functional gates allows an efficient implementation of components at a higher level of abstraction. In several classes of applications which typically involve RT level oriented design approach, these components can circumvent various issues related to synthesis of multifunctional circuits at the gate level. While the synthesis at the gate level is difficult, at RT level a skilled designer is still able to design a far more complex circuits by himself. If a set of efficient bi-functional RTL components is available, their utilization is expected to improve efficiency of the resulting circuit. In this paper, validity of this assumption is demonstrated through a design of bi-functional adder/subtractor circuit. At the gate level, one-bit full adder/subtractor circuit was created and optimised. This circuit was subsequently utilised for design of multi-bit adder/subtractor which was successfully simulated at the transistor level with MOSFET implementation of bi-functional logic gates. Besides adder/subtractor, an increment/decrement RTL component is also presented.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
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OECD FORD branch
20206 - Computer hardware and architecture
Result continuities
Project
<a href="/en/project/LQ1602" target="_blank" >LQ1602: IT4Innovations excellence in science</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach
Others
Publication year
2018
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
2018 New Generation of CAS (NGCAS)
ISBN
978-1-5386-7680-6
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
25-28
Publisher name
IEEE Circuits and Systems Society
Place of publication
Valletta
Event location
Valletta, Malta
Event date
Nov 20, 2018
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000461061000007