Evolutionary Functional Approximation of Circuits Implemented into FPGAs

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F16%3APU121666" target="_blank" >RIV/00216305:26230/16:PU121666 - isvavai.cz</a>

Result on the web

<a href="http://www.fit.vutbr.cz/research/pubs/all.php?id=11243" target="_blank" >http://www.fit.vutbr.cz/research/pubs/all.php?id=11243</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/SSCI.2016.7850173" target="_blank" >10.1109/SSCI.2016.7850173</a>

Result language

angličtina

Original language name

Evolutionary Functional Approximation of Circuits Implemented into FPGAs

Original language description

In many applications it is acceptable to allow a small error in the result if significant improvements are obtained in terms of performance, area or energy efficiency. Exploiting this principle is particularly important for FPGA-based solutions that are inherently subject to many resources- oriented constraints. This paper devises an automated method that enables to approximate circuit components which are often implemented in multiple instances in FPGA-based accelerators. The approximation process starts with a fully functional gate-level circuit, which is approximated by means of Cartesian Genetic Programming reflecting the error metric and constraints formulated by the user. The evolved circuits are then implemented for a particular FPGA by common FPGA synthesis and optimization tools. It is shown using five different FPGA tools, that the approximations obtained by CGP working at the gate level are preserved at the level look-up tables of FPGAs. The proposed method is evaluated in the task of 8-bit adder, 8-bit multiplier, 9-input median and 25-input median approximation. 

Czech name

—

Czech description

—

Type

D - Article in proceedings

CEP classification

—

OECD FORD branch

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Project

Result was created during the realization of more than one project. More information in the Projects tab.

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year

2016

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

2016 IEEE Symposium Series on Computational Intelligence

ISBN

978-1-5090-4240-1

ISSN

—

e-ISSN

—

Number of pages

8

Pages from-to

1-8

Publisher name

Institute of Electrical and Electronics Engineers

Place of publication

Athens

Event location

Athens

Event date

Dec 6, 2016

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

000400488302079