Search-based synthesis of approximate circuits implemented into FPGAs

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F16%3APU121614" target="_blank" >RIV/00216305:26230/16:PU121614 - isvavai.cz</a>

Result on the web

<a href="http://ieeexplore.ieee.org/document/7577305/" target="_blank" >http://ieeexplore.ieee.org/document/7577305/</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/FPL.2016.7577305" target="_blank" >10.1109/FPL.2016.7577305</a>

Result language

angličtina

Original language name

Search-based synthesis of approximate circuits implemented into FPGAs

Original language description

Approximate computing is capable of exploiting the error resilience of various applications with the aim of improving their parameters such as performance, energy consumption and area on a chip. In this paper, a new systematic approach for the approximation and optimization of circuits intended for LUT-based field programmable gate arrays (FPGAs) is proposed. In order to deliver a good trade-off between the quality of processing and implementation cost, the method employs a genetic programming-based optimization engine. The circuits are internally represented and optimized at the gate level. The resulting LUT-based netlists are obtained using a commercial FPGA tool. In the experimental part, four commonly available commercial FPGA design tools (Xilinx ISE, Xilinx Vivado, Precision, and Quartus) and state-of-the-art academia circuit synthesis and optimization tool ABC are compared. The quality of approximated circuits is evaluated using relaxed equivalence checking by means of Binary decision diagrams. An important conclusion is that the improvements (i.e. area reductions) at the gate level are preserved by the FPGA design tools and thus the number of LUTs is also adequately reduced. It was shown that the current state-of-the-art synthesis tools provide (for some instances) the results that are far from an optimum. For example, a 40% reduction (68 LUTs) was achieved for 'clmb' benchmark circuit (Bus Interface) without introducing any error. Additional 43% reduction can be obtained by introducing only a 0.1% error.

Czech name

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Czech description

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Type

D - Article in proceedings

CEP classification

—

OECD FORD branch

20206 - Computer hardware and architecture

Project

<a href="/en/project/GA14-04197S" target="_blank" >GA14-04197S: Advanced Methods for Evolutionary Design of Complex Digital Circuits</a><br>

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year

2016

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

26th International Conference on Field Programmable Logic and Applications

ISBN

978-2-8399-1844-2

ISSN

—

e-ISSN

—

Number of pages

4

Pages from-to

1-4

Publisher name

Institute of Electrical and Electronics Engineers

Place of publication

Lausanne

Event location

Lausanne

Event date

Aug 29, 2016

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

000386610400007