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Parity Waterfall Method

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F16%3A00242840" target="_blank" >RIV/68407700:21240/16:00242840 - isvavai.cz</a>

  • Result on the web

    <a href="http://dx.doi.org/10.1109/DDECS.2016.7482441" target="_blank" >http://dx.doi.org/10.1109/DDECS.2016.7482441</a>

  • DOI - Digital Object Identifier

    <a href="http://dx.doi.org/10.1109/DDECS.2016.7482441" target="_blank" >10.1109/DDECS.2016.7482441</a>

Alternative languages

  • Result language

    angličtina

  • Original language name

    Parity Waterfall Method

  • Original language description

    This paper proposes a method for improvement of the fault-coverage capabilities of Field Programmable Gate Array (FPGA) designs. It utilizes Concurrent Error Detection (CED) techniques and the basic architectures of actual modern FPGAs the Look-Up Table (LUT) with two outputs. Proposed Parity Waterfall method is based on a cascade (waterfall) of several waves of inner parity generating the final parity of outputs of the whole circuit. The utilization of the (mostly) unused output of a two-output LUT allows the proposed method to cover any single possible routing or LUT fault with a small area overhead. The method is experimentally evaluated using the standard set of IWLS2005 benchmarks and using our simulator/emulator. The experimental results of the proposed parity waterfall method are compared with a similar existing technique (duplication with comparison). These results show that the area overhead is smaller than the overhead of the duplication with comparison method for all of the tested circuits and 100% fault coverage is achieved.

  • Czech name

  • Czech description

Classification

  • Type

    D - Article in proceedings

  • CEP classification

    JC - Computer hardware and software

  • OECD FORD branch

Result continuities

  • Project

    Result was created during the realization of more than one project. More information in the Projects tab.

  • Continuities

    P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Others

  • Publication year

    2016

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Article name in the collection

    Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)

  • ISBN

    978-1-5090-2467-4

  • ISSN

    2334-3133

  • e-ISSN

  • Number of pages

    6

  • Pages from-to

    21-26

  • Publisher name

    IEEE

  • Place of publication

    Piscataway

  • Event location

    Košice

  • Event date

    Apr 20, 2016

  • Type of event by nationality

    WRD - Celosvětová akce

  • UT code for WoS article

    000387091100004