Faults Coverage Improvement based on Fault Simulation and Partial Duplication

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F10%3A00169332" target="_blank" >RIV/68407700:21240/10:00169332 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Faults Coverage Improvement based on Fault Simulation and Partial Duplication
Original language description
A method how to improve the coverage of single faults in combinational circuits is proposed. The method is based on Concurrent Error Detection, but uses a fault simulation to find Critical points - the places, where faults are difficult to detect. The partial duplication of the design with regard to these critical points is able to increase the faults coverage with a low area overhead cost. Due to higher fault coverage we can increase the dependability parameters. The proposed modification is tested onthe railway station safety devices designs implemented in the FPGA.
Czech name
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Czech description
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Project
<a href="/en/project/GA102%2F09%2F1668" target="_blank" >GA102/09/1668: SoC circuits reliability and availability improvement</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)<br>S - Specificky vyzkum na vysokych skolach

Publication year
2010
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of the 13th Euromicro Conference on Digital System Design
ISBN
978-0-7695-4171-6
ISSN
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e-ISSN
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Number of pages
7
Pages from-to
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Publisher name
IEEE Computer Society Press
Place of publication
Los Alamitos
Event location
Lille
Event date
Sep 1, 2010
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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