Evaluation of the SEU Faults Coverage of a Simple Fault Model for Application-Oriented FPGA Testing

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F20%3A00342223" target="_blank" >RIV/68407700:21240/20:00342223 - isvavai.cz</a>
Result on the web
<a href="https://doi.org/10.1109/DSD51259.2020.00111" target="_blank" >https://doi.org/10.1109/DSD51259.2020.00111</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/DSD51259.2020.00111" target="_blank" >10.1109/DSD51259.2020.00111</a>

Result language
angličtina
Original language name
Evaluation of the SEU Faults Coverage of a Simple Fault Model for Application-Oriented FPGA Testing
Original language description
Testing of FPGA-based designs persists to be a challenging task because of the complex FPGA architecture with heterogeneous components, and therefore a complicated fault model. The standard stuck-at fault model has been found insufficient. On the other hand, very precise FPGA fault models have been recently devised. However, these models are often excessively complex and require a lot of resources (run-time, memory) to manipulate with. In this paper, we propose a simple yet efficient combined fault model comprising bit-flips in look-up tables and stuck-at faults in the rest of logic. On~top of this model, a dedicated SAT-based application-oriented ATPG has been designed. The main contribution of this paper is the evaluation of efficiency of the fault model with the respective ATPG by exhaustive hardware emulation of all possible SEUs in the configuration memory that may influence the functionality of the circuit implemented in the FPGA. We show that the obtained fault coverage reaches up to more than 99%, which makes the method applicable in practice. Even though combinational circuits are assumed only, the method can be used to quickly test safety-critical combinational cores.
Czech name
—
Czech description
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Project
<a href="/en/project/EF16_019%2F0000765" target="_blank" >EF16_019/0000765: Research Center for Informatics</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Publication year
2020
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of the 23rd Euromicro Conference on Digital Systems Design
ISBN
978-1-7281-9535-3
ISSN
—
e-ISSN
—
Number of pages
8
Pages from-to
684-691
Publisher name
IEEE Computer Soc.
Place of publication
Los Alamitos, CA
Event location
Virtual Event organized from Kranj, Slovenia
Event date
Aug 26, 2020
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000630443300100

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