SAT-ATPG for Application-Oriented FPGA Testing

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F16%3A00301987" target="_blank" >RIV/68407700:21240/16:00301987 - isvavai.cz</a>
Result on the web
<a href="http://ieeexplore.ieee.org/document/7743734/" target="_blank" >http://ieeexplore.ieee.org/document/7743734/</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/BEC.2016.7743734" target="_blank" >10.1109/BEC.2016.7743734</a>

Result language
angličtina
Original language name
SAT-ATPG for Application-Oriented FPGA Testing
Original language description
In this paper we propose a SAT-based ATPG algorithm for application-oriented FPGA testing. For this purpose, a novel fault model is introduced which combines the stuck-at fault model for interconnects testing with the bit-flip model for LUT testing. The concept of SAT-based ATPG enables integrating these two models easily. Fault coverage and fault dominance of the two models is discussed in this paper, yielding suggestions for using the proposed combined model.
Czech name
—
Czech description
—

Project
<a href="/en/project/GA16-05179S" target="_blank" >GA16-05179S: Fault-Tolerant and Attack-Resistant Architectures Based on Programmable Devices: Research of Interplay and Common Features</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year
2016
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of the 15th Biennial Baltic Electronics Conference
ISBN
978-1-5090-1393-7
ISSN
1736-3705
e-ISSN
—
Number of pages
4
Pages from-to
83-86
Publisher name
Tallin University of Technology
Place of publication
Tallin
Event location
Tallinn
Event date
Oct 3, 2016
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000390684300018

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