Fault-tolerant and fail-safe design based on reconfiguration

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F11%3A00179457" target="_blank" >RIV/68407700:21240/11:00179457 - isvavai.cz</a>
Result on the web
<a href="http://www.igi-global.com/embeddedcontent.aspx?PageCode=WGSLd" target="_blank" >http://www.igi-global.com/embeddedcontent.aspx?PageCode=WGSLd</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.4018/978-1-60960-212-3" target="_blank" >10.4018/978-1-60960-212-3</a>

Result language
angličtina
Original language name
Fault-tolerant and fail-safe design based on reconfiguration
Original language description
The main aim of this chapter is to present the way, how to design fault-tolerant or fail-safe systems in programmable hardware (FPGAs) and therefore to use FPGAs in mission-critical applications, too. RAM based FPGAs are usually taken for unreliable dueto high probability of transient faults (SEU) and therefore inapplicable in this area. But FPGAs can be easily reconfigured. Our aim is to utilize appropriate type of FPGA reconfiguration and to combine it with well-known methods for fail-safe and fault-tolerant design (duplex, TMR) including on-line testing methods for fault detection and then startup of the reconfiguration process. Dependability parameters' calculations based on reliability models is integral part of proposed methodology. The trade-off between the requested level of dependability characteristics of a designed system and area overhead with respect to FPGA possible faults is main property and advantage of proposed methodology.
Czech name
—
Czech description
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Project
<a href="/en/project/GA102%2F09%2F1668" target="_blank" >GA102/09/1668: SoC circuits reliability and availability improvement</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year
2011
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

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