Methodology for Design of Highly Dependable Systems in FPGA

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F10%3APU89555" target="_blank" >RIV/00216305:26230/10:PU89555 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Methodology for Design of Highly Dependable Systems in FPGA
Original language description
In the paper, a survey of our research activities the goal of which is to develop a methodology allowing to design highly dependable system in FPGA is described. First, our experiences with partial dynamic reconfiguration in FPGA and application of partial reconfiguration as advanced solution for constructing of different types of fault tolerant architectures are described. Secondly, the main principles of methodology and first experiments with real fault tolerant designs based on partial dynamic reconfiguration implemented into Virtex5 and latest Virtex6 FPGAs are demonstrated.<br>
Czech name
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Czech description
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Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)<br>S - Specificky vyzkum na vysokych skolach

Publication year
2010
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
International Scientific Conference on Computer Science and Engineering
ISBN
978-80-8086-164-3
ISSN
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e-ISSN
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Number of pages
8
Pages from-to
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Publisher name
The University of Technology Košice
Place of publication
Košice
Event location
Stará Ľubovňa
Event date
Sep 20, 2010
Type of event by nationality
EUR - Evropská akce
UT code for WoS article
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