Fault Tolerant Structure for SRAM-based FPGA via Partial Dynamic Reconfiguration
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F10%3APU89530" target="_blank" >RIV/00216305:26230/10:PU89530 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Fault Tolerant Structure for SRAM-based FPGA via Partial Dynamic Reconfiguration
Original language description
<p align=left>In this paper, activities which aim at developing a methodology of fault tolerant systems design into SRAM-based FPGA platforms with different types of diagnostic approaches are presented. Basic principles of partial dynamic reconfigurationare described together with their impact on the fault tolerance of the digital design in FPGA. A generic controller for driving dynamic reconfiguration process of faulty unit is demonstrated and analyzed. Parameters of the generic partial reconfiguration controller are experimentally verified. The developed controller is compared with other approaches based on micro-controllers inside FPGA. A structure which can be used in fault tolerant system design into SRAM-based FPGA using partial reconfigurationcontroller is then described. The presented structure is proven fully functional on the ML506 development board for different types of RTL components.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)<br>S - Specificky vyzkum na vysokych skolach
Others
Publication year
2010
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
13th EUROMICRO Conference on Digital System Design, DSD'2010
ISBN
978-0-7695-4171-6
ISSN
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e-ISSN
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Number of pages
8
Pages from-to
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Publisher name
IEEE Computer Society
Place of publication
Lille
Event location
Lille
Event date
Sep 1, 2010
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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