Parity driven reconfigurable duplex system
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F17%3A00313345" target="_blank" >RIV/68407700:21240/17:00313345 - isvavai.cz</a>
Result on the web
<a href="http://dx.doi.org/10.1016/j.micpro.2017.06.015" target="_blank" >http://dx.doi.org/10.1016/j.micpro.2017.06.015</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1016/j.micpro.2017.06.015" target="_blank" >10.1016/j.micpro.2017.06.015</a>
Alternative languages
Result language
angličtina
Original language name
Parity driven reconfigurable duplex system
Original language description
This paper proposes a method improving the fault-coverage capabilities of Field Programmable Gate Array (FPGA) designs. Faults are mostly Single Event Upsets (SEUs) in the configuration memory of SRAM-based FPGAs and they can change the functionality of an implemented design. These changes may lead to crucial mistakes and cause damage to people and environment. The proposed method utilizes Concurrent Error Detection techniques and the basic architectures of actual modern FPGAs - the Look-Up Table (LUT) with two outputs. The main part of the paper is the description of the proposed method (Parity Waterfall) based on a cascade - waterfall - of several waves of inner parity generating the final parity of outputs of the whole circuit. The proposed Parity Waterfall (PWtf) method utilizes the (mostly) unused output of a two-output LUT to cover any single possible routing or LUT fault with a small area overhead. The encapsulation of the proposed PWtf method into a Duplication with Comparison scheme is presented in the second part of the paper. This encapsulation allows us to create a system containing two independent copies of all parts able to detect and localize any single fault (like common Triple Modular Redundancy method). Experiments are performed on the standard set of IWLS2005 benchmarks in our simulator. The results demonstrate differences between our proposed method and a similar existing technique - Duplication with Comparison (DwC), and between the encapsulated PWtf method and TMR. The proposed method has a lower relative overhead and requires a lower number of inputs and outputs.
Czech name
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Czech description
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Classification
Type
J<sub>imp</sub> - Article in a specialist periodical, which is included in the Web of Science database
CEP classification
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OECD FORD branch
20206 - Computer hardware and architecture
Result continuities
Project
<a href="/en/project/GA16-05179S" target="_blank" >GA16-05179S: Fault-Tolerant and Attack-Resistant Architectures Based on Programmable Devices: Research of Interplay and Common Features</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2017
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Name of the periodical
Microprocessors and Microsystems
ISSN
0141-9331
e-ISSN
1872-9436
Volume of the periodical
52
Issue of the periodical within the volume
July
Country of publishing house
NL - THE KINGDOM OF THE NETHERLANDS
Number of pages
10
Pages from-to
251-260
UT code for WoS article
000407984000021
EID of the result in the Scopus database
2-s2.0-85021187832