Reconfigurable Duplex System Increasing Fault Tolerance for Circuits Based on FPGAs

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F05%3A03109883" target="_blank" >RIV/68407700:21230/05:03109883 - isvavai.cz</a>

Result on the web

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DOI - Digital Object Identifier

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Result language

angličtina

Original language name

Reconfigurable Duplex System Increasing Fault Tolerance for Circuits Based on FPGAs

Original language description

Our paper describes a new structure of design for FPGAs which improves reliability parameters and preserves lower area overhead than the classical methods such as duplication or triplication. Our solution assumes the possibility of dynamic reconfiguration of the faulty part. The most important criterion is the speed of the fault detection and the safety of the whole circuit with respect to the surrounding environment. Our methodology enables cooperation between on-line methods and off-line BIST methodsfor fault detection and localization.

Czech name

Reconfigurable Duplex System Increasing Fault Tolerance for Circuits Based on FPGAs

Czech description

Není k dispozici

Type

D - Article in proceedings

CEP classification

JC - Computer hardware and software

OECD FORD branch

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Project

<a href="/en/project/GA102%2F03%2F0672" target="_blank" >GA102/03/0672: Research of methods and tools for verification of embedded computer system fault tolerance</a><br>

Continuities

Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year

2005

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

Proceedings of the Work in Progress Session

ISBN

3-902457-09-0

ISSN

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e-ISSN

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Number of pages

2

Pages from-to

13-14

Publisher name

Johannes Kepler University

Place of publication

Linz

Event location

Porto

Event date

Aug 30, 2005

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

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