High Reliable FPGA Based System Design Methodology
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F04%3A03099661" target="_blank" >RIV/68407700:21230/04:03099661 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
High Reliable FPGA Based System Design Methodology
Original language description
This paper describes a methodology of the automatic design process for the concurrent error detection (CED) circuits based on FPGAs. Our solution assumes the possibility of dynamical reconfiguration of the faulty part. The most important criterion is thespeed of the fault detection and the safety of the whole circuit with respect to the surrounding environment. Our methodology enables cooperation between on-line and off-line BIST for fault detection and localization.
Czech name
Není k dispozici
Czech description
Není k dispozici
Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
<a href="/en/project/GA102%2F04%2F2137" target="_blank" >GA102/04/2137: Design of highly reliable control systems built on dynamically reconfigurable FPGAs.</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2004
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Work in Progress Session of 30th EUROMICRO and DSD 2004
ISBN
3-902457-05-8
ISSN
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e-ISSN
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Number of pages
2
Pages from-to
30-31
Publisher name
Universität Linz
Place of publication
Linz
Event location
Rennes
Event date
Aug 31, 2004
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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