Synthesis of approximate circuits for LUT-based FPGAs

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F21%3APU139369" target="_blank" >RIV/00216305:26230/21:PU139369 - isvavai.cz</a>

Result on the web

<a href="https://www.fit.vut.cz/research/publication/12453/" target="_blank" >https://www.fit.vut.cz/research/publication/12453/</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/DDECS52668.2021.9417066" target="_blank" >10.1109/DDECS52668.2021.9417066</a>

Result language

angličtina

Original language name

Synthesis of approximate circuits for LUT-based FPGAs

Original language description

Approximate computing is an emerging paradigm that trades the accuracy of computation to achieve gain in terms of design area, critical path delay and/or power consumption. There is a rich body of literature showing that the approximate hardware components serving as basic building blocks for energy-efficient implementation of complex systems offer a remarkable gain in efficiency and/or performance in exchange for small losses in output quality. However, recent studies revealed that the approximate components optimized mainly for ASICs offer asymmetric gain when used in FPGAs. In this work, we present an iterative design method for automated synthesis of elementary approximate components natively optimized for usage in LUT-based FPGAs. The method takes into account the number of LUTs and LUT-level propagation delay instead of the number of gates and logic levels typically considered in other works. Using this method, we synthesized various approximate adders (up to 64-bit) and multipliers (8-bit and 16-bit). Compared to the current state-of-the-art, our designs achieve better trade-off when considered the worst case absolute error, number of LUTs and propagation delay. The discovered approximate adders and multipliers are available online in the form of Verilog netlists consisting of 4, 5 and 6-input LUTs.

Czech name

—

Czech description

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Type

D - Article in proceedings

CEP classification

—

OECD FORD branch

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Project

<a href="/en/project/GA19-10137S" target="_blank" >GA19-10137S: Designing and exploiting libraries of approximate circuits</a><br>

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year

2021

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

24th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)

ISBN

978-1-6654-3595-6

ISSN

—

e-ISSN

—

Number of pages

6

Pages from-to

17-22

Publisher name

IEEE Computer Society

Place of publication

Vienna

Event location

Vídeň

Event date

Apr 7, 2021

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

000672620200004