Role of circuit representation in evolutionary design of energy-efficient approximate circuits

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F18%3APU130684" target="_blank" >RIV/00216305:26230/18:PU130684 - isvavai.cz</a>

Result on the web

<a href="http://digital-library.theiet.org/content/journals/10.1049/iet-cdt.2017.0188" target="_blank" >http://digital-library.theiet.org/content/journals/10.1049/iet-cdt.2017.0188</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1049/iet-cdt.2017.0188" target="_blank" >10.1049/iet-cdt.2017.0188</a>

Result language

angličtina

Original language name

Role of circuit representation in evolutionary design of energy-efficient approximate circuits

Original language description

Circuit approximation has been introduced in recent years as a viable method for constructing energy-efficient electronic systems. An open problem is how to effectively obtain approximate circuits showing good compromises between key circuit parameters - the error, power consumption, area and delay. The use of evolutionary algorithms in the task of circuit approximation has led to promising results. Unfortunately, only relatively small circuit instances have been tackled because of the scalability problems of the evolutionary design method. This study demonstrates how to push the limits of the evolutionary design by choosing a more suitable representation on the one hand and a more efficient fitness function on the other hand. In particular, the authors show that employing full adders as building blocks leads to more efficient approximate circuits. The authors focused on the approximation of key arithmetic circuits such as adders and multipliers. While the evolutionary design of adders represents a rather easy benchmark problem, the design of multipliers is known to be one of the hardest problems. The authors evolved a comprehensive library of energy-efficient 12-bit multipliers with a guaranteed worst-case error. The library consists of 65 Pareto dominant solutions considering power, delay, area and error as design objectives.

Czech name

—

Czech description

—

Type

J_imp - Article in a specialist periodical, which is included in the Web of Science database

CEP classification

—

OECD FORD branch

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Project

<a href="/en/project/GA16-17538S" target="_blank" >GA16-17538S: Relaxed equivalence checking for approximate computing</a><br>

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year

2018

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Name of the periodical

IET Computers and Digital Techniques

ISSN

1751-8601

e-ISSN

1751-861X

Volume of the periodical

2018

Issue of the periodical within the volume

4

Country of publishing house

GB - UNITED KINGDOM

Number of pages

11

Pages from-to

139-149

UT code for WoS article

000436957700004

EID of the result in the Scopus database

2-s2.0-85049405511