Testing PCBs Based on Boundary Scan

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F03%3APU42562" target="_blank" >RIV/00216305:26230/03:PU42562 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Testing PCBs Based on Boundary Scan
Original language description
The paper describes a practical approach to testing PCBs with Xilinx FPGAs. The approach is based on a PCB netlist analysis, which is revealing the existing connections on the PCB through the Boundary Scan chain and comparing the two results. It is alsosupposed that the developed software tools will be used for debugging PCBs with Xilinx FPGAs. The goal of the research activities is to develop an easy to use an efficient and user- friendly software tools.
Czech name
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Czech description
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Project
<a href="/en/project/GA102%2F01%2F1531" target="_blank" >GA102/01/1531: Formal approaches in digital circuit diagnostics - testable design verification</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year
2003
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of International Carpathian Control Conference
ISBN
80-7099-509-2
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
119-122
Publisher name
The University of Technology Košice
Place of publication
Košice
Event location
Vysoké Tatry
Event date
May 26, 2003
Type of event by nationality
EUR - Evropská akce
UT code for WoS article
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