Test scheduling for embedded systems

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F03%3APU42590" target="_blank" >RIV/00216305:26230/03:PU42590 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Test scheduling for embedded systems
Original language description
The paper proposes two approaches to test scheduling. The first one utilizes the concept of TACG (Test Application Conflict Graph). For the testing process the resource utilization model is defined and used for the TACG construction. Different conflictsthat must be taken into account during test scheduling are presented. The paper offers a methodology that can be utilized during embedded test design process, the final goal of which is to reduce the overall test application time and power consumption duuring the test application. The second methodology is based on optimising the test schedule - the test application time, TAM width and power consumption are taken into account during the process. The goal of the methodology is a reasonable trade-off between these parameters.
Czech name
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Czech description
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Project
<a href="/en/project/GA102%2F01%2F1531" target="_blank" >GA102/01/1531: Formal approaches in digital circuit diagnostics - testable design verification</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year
2003
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings EUROMICRO Symposium on Digital System Design - Architectures, Methods and Tools DSD 2003
ISBN
0-7695-2003-0
ISSN
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e-ISSN
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Number of pages
5
Pages from-to
463-467
Publisher name
IEEE Computer Society Press
Place of publication
Belek
Event location
Belek
Event date
Sep 2, 2003
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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