Checker Design for On-line Testing of Xilinx FPGA Communication
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F07%3APU70809" target="_blank" >RIV/00216305:26230/07:PU70809 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Checker Design for On-line Testing of Xilinx FPGA Communication
Original language description
<p align=left>In the paper, a methodology of developing checkers for communication protocol testing is presented. It was used to develop checker to test IP cores communication protocol implemented in Xilinx FPGA based designs. A formal language enablingto describe the protocol was created for this purpose together with a generator of the formal description into VHDL code. The VHDL code can be then used for the synthesis of the checker structure and used in applications with Xilinx FPGAs.
Czech name
Checker Design for On-line Testing of Xilinx FPGA Communication
Czech description
<p align=left>In the paper, a methodology of developing checkers for communication protocol testing is presented. It was used to develop checker to test IP cores communication protocol implemented in Xilinx FPGA based designs. A formal language enablingto describe the protocol was created for this purpose together with a generator of the formal description into VHDL code. The VHDL code can be then used for the synthesis of the checker structure and used in applications with Xilinx FPGAs.
Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
<a href="/en/project/GD102%2F05%2FH050" target="_blank" >GD102/05/H050: Integrated Approach to Education of PhD Students in the Area of Parallel and Distributed Systems</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2007
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
The 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
ISBN
0-7695-2885-6
ISSN
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e-ISSN
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Number of pages
9
Pages from-to
152-160
Publisher name
IEEE Computer Society
Place of publication
Rome
Event location
Rome
Event date
Sep 26, 2007
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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