Checker for Communication Protocol between IP Cores Based on FPGA

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F07%3APU70895" target="_blank" >RIV/00216305:26230/07:PU70895 - isvavai.cz</a>

Result on the web

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DOI - Digital Object Identifier

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Result language

angličtina

Original language name

Checker for Communication Protocol between IP Cores Based on FPGA

Original language description

In the paper, the principles of a unit design which can be used for on-line communication protocol checking is presented. It is shown how the checker can be used to check the communication between IP cores implemented in FPGA. The communication must be precisely defined - for this purpose, a formal approach was developed which allows to describe ambiguously the conditions which must be satisfied during the communication. From the description, the checker description in VHDL is generated (a compiler wasdeveloped for this purpose) and implemented into FPGA. The checker watches the communication and detects such states which do not satisfy protocol definitions. If such a situation appears, it is indicated that hardware implementation does not work properly. The methodology was verified on LocalLink communication protocol developed by Xilinx, Virtex 2 Pro FPGA was used for the implementation. Future research will be directed towards the development of fault tolerant systems<br>design meth

Czech name

Checker for Communication Protocol between IP Cores Based on FPGA

Czech description

In the paper, the principles of a unit design which can be used for on-line communication protocol checking is presented. It is shown how the checker can be used to check the communication between IP cores implemented in FPGA. The communication must be precisely defined - for this purpose, a formal approach was developed which allows to describe ambiguously the conditions which must be satisfied during the communication. From the description, the checker description in VHDL is generated (a compiler wasdeveloped for this purpose) and implemented into FPGA. The checker watches the communication and detects such states which do not satisfy protocol definitions. If such a situation appears, it is indicated that hardware implementation does not work properly. The methodology was verified on LocalLink communication protocol developed by Xilinx, Virtex 2 Pro FPGA was used for the implementation. Future research will be directed towards the development of fault tolerant systems<br>design meth

Type

D - Article in proceedings

CEP classification

JC - Computer hardware and software

OECD FORD branch

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Project

<a href="/en/project/GD102%2F05%2FH050" target="_blank" >GD102/05/H050: Integrated Approach to Education of PhD Students in the Area of Parallel and Distributed Systems</a><br>

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year

2007

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

3rd Doctoral Workshop on Mathematical and Engineering Methods in Computer Science

ISBN

978-80-7355-077-6

ISSN

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e-ISSN

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Number of pages

8

Pages from-to

193-200

Publisher name

Faculty of Informatics MU

Place of publication

Znojmo

Event location

Znojmo

Event date

Oct 26, 2007

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

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