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Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F08%3APU76700" target="_blank" >RIV/00216305:26230/08:PU76700 - isvavai.cz</a>

  • Result on the web

  • DOI - Digital Object Identifier

Alternative languages

  • Result language

    angličtina

  • Original language name

    Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration

  • Original language description

    In this paper, a new concept which allows the reduction of test vectors volume is presented. The concept is based on reconfiguration of some gates of circuit under test. Instead of testing the original circuit, a circuit which has the same topology (butsome of its gate functions are reconfigured) is actually tested. Two possible implementations of the reconfiguration are investigated. Preliminary experiments indicate that test length can be reduced to approx. 70% of its initial value while the increasein transistors is moderate.

  • Czech name

    Redukce počtu testovacích vektorů pomocí rekonfigurace na úrovni hradel

  • Czech description

    Článek popisuje způsob umožňující snížit počet testovacích&nbsp;vektorů číslicového obvodu pomocí rekonfigurace některých hradel obvodu. Rekonfigurace je provedena před tím, než je aplikována posloupnost testovacích vektorů. První experimenty ukazují, žeje možné snížit počet testovacích vektorů na 70% původní hodnoty.

Classification

  • Type

    D - Article in proceedings

  • CEP classification

    JC - Computer hardware and software

  • OECD FORD branch

Result continuities

  • Project

    <a href="/en/project/GA102%2F06%2F0599" target="_blank" >GA102/06/0599: Methods of polymorphic digital circuit design</a><br>

  • Continuities

    Z - Vyzkumny zamer (s odkazem do CEZ)

Others

  • Publication year

    2008

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Article name in the collection

    Proc. of 2008 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop

  • ISBN

    978-1-4244-2276-0

  • ISSN

  • e-ISSN

  • Number of pages

    4

  • Pages from-to

  • Publisher name

    IEEE Computer Society

  • Place of publication

    Bratislava

  • Event location

    Bratislava

  • Event date

    Apr 16, 2008

  • Type of event by nationality

    WRD - Celosvětová akce

  • UT code for WoS article