An evaluation of the application dependent FPGA test method

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F46747885%3A24220%2F12%3A%230002019" target="_blank" >RIV/46747885:24220/12:#0002019 - isvavai.cz</a>
Result on the web
<a href="http://apps.webofknowledge.com/full_record.do?product=WOS&search_mode=GeneralSearch&qid=10&SID=W1INN4fIFD5m8h3IIim&page=1&doc=2" target="_blank" >http://apps.webofknowledge.com/full_record.do?product=WOS&search_mode=GeneralSearch&qid=10&SID=W1INN4fIFD5m8h3IIim&page=1&doc=2</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/DDECS.2012.6219017" target="_blank" >10.1109/DDECS.2012.6219017</a>

Result language
angličtina
Original language name
An evaluation of the application dependent FPGA test method
Original language description
In this paper we evaluate the application dependent FPGA (Field Programmable Gate Array) test method which uses an ASIC BIST (Application Specific Integrated Circuit Built-in Self-Test) techniques and tools and efficiently utilizes the properties of nowadays FPGA devices, such as the partial runtime reconfiguration. The method splits the tested circuit and then uses partial reconfiguration to change the role of the partitioned modules, which may act as testers or as response analyzers. Circuit partitions are translated to an ATPG (Automatic Test Pattern Generator) readable format and the deterministic test vectors are generated. The compression tool is used to compress test patterns, thus it is not required to create additional test access interfaces or to use multiple reconfigurations. We show that the usage of the method reduces test time and memory requirements and it leads to good test coverage results. Each step of the design flow is described and evaluated in detail as well as th
Czech name
—
Czech description
—

Publication year
2012
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2012
ISBN
978-1-4673-1187-8
ISSN
—
e-ISSN
—
Number of pages
4
Pages from-to
22-25
Publisher name
IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA
Place of publication
—
Event location
Tallinn, ESTONIA
Event date
Apr 18, 2012
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000312905700011

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