Application dependent FPGA testing method using compressed deterministic test vectors
Result description
Tests that exercise complete FPGA resources are often more time and memory consuming than application dependent tests due to the high number of reconfigurations required for complete test. Presented application dependent test does not require reconfiguration of the tested hardware, thus it preserves conditions that led to the erroneous behavior of the FPGA device. The test method saves time and memory requirements of the test by storing compressed test patterns into the internal structure of the FPGA. The patterns are obtained with the help of the improved COMPAS algorithm - compression system based on test pattern overlapping. The COMPAS requires unused scan chains for the test pattern decompression. This is well suited for nowadays FPGAs which contain high number of LUT based shift registers. The neighborhood of the tested circuit is dynamically reconfigured into TPG and ORA. The TPG contains compressed test patterns which allow fast test pattern decompression. The paper demonstrates
Keywords
The result's identifiers
Result code in IS VaVaI
Result on the web
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=5560208
DOI - Digital Object Identifier
Alternative languages
Result language
angličtina
Original language name
Application dependent FPGA testing method using compressed deterministic test vectors
Original language description
Tests that exercise complete FPGA resources are often more time and memory consuming than application dependent tests due to the high number of reconfigurations required for complete test. Presented application dependent test does not require reconfiguration of the tested hardware, thus it preserves conditions that led to the erroneous behavior of the FPGA device. The test method saves time and memory requirements of the test by storing compressed test patterns into the internal structure of the FPGA. The patterns are obtained with the help of the improved COMPAS algorithm - compression system based on test pattern overlapping. The COMPAS requires unused scan chains for the test pattern decompression. This is well suited for nowadays FPGAs which contain high number of LUT based shift registers. The neighborhood of the tested circuit is dynamically reconfigured into TPG and ORA. The TPG contains compressed test patterns which allow fast test pattern decompression. The paper demonstrates
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
GA102/09/1668: SoC circuits reliability and availability improvement
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2010
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
2010 IEEE 16th International On-Line Testing Symposium (IOLTS)
ISBN
978-1-4244-7724-1
ISSN
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e-ISSN
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Number of pages
2
Pages from-to
192-193
Publisher name
IEEE
Place of publication
Atheny
Event location
Corfu
Event date
Jan 1, 2010
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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Result type
D - Article in proceedings
CEP
JC - Computer hardware and software
Year of implementation
2010