Structural Test of Programmed FPGA Circuits

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F46747885%3A24220%2F09%3A%230001334" target="_blank" >RIV/46747885:24220/09:#0001334 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Structural Test of Programmed FPGA Circuits
Original language description
We present a new concept of the test method for FPGA devices. Instead of being focused on structural test of the device, the method tests logic and interconnection resources of the FPGA, that are actually used by implemented circuit. The method is basedon reconfiguration ability of nowadays FPGAs and utilizes test vectors originally created for ASIC circuits. We present an idea of circuit partitioning and a transcription scheme, that converts the FPGA netlist to the ASIC one. Preliminary results of test patterns efficiency on transformed benchmark circuits are presented.
Czech name
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Czech description
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Project
<a href="/en/project/GA102%2F09%2F1668" target="_blank" >GA102/09/1668: SoC circuits reliability and availability improvement</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year
2009
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
PROCEEDINGS OF THE 2009 IEEE SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS
ISBN
978-1-4244-3339-1
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
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Publisher name
IEEE COMPUTER SOC
Place of publication
CZECH REPUBLIC
Event location
CZECH REPUBLIC, Liberec
Event date
Jan 1, 2009
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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