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Taylor Series Numerical Integrator

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F08%3APU76790" target="_blank" >RIV/00216305:26230/08:PU76790 - isvavai.cz</a>

  • Result on the web

  • DOI - Digital Object Identifier

Alternative languages

  • Result language

    angličtina

  • Original language name

    Taylor Series Numerical Integrator

  • Original language description

    The simulation language TKSL and Modern Taylor Series Method have proved to be very powerful computing tools for extremely exact, stable and fast numerical solutions of systems of differential equations. In a natural way, TKSL also involves solutions ofproblems that can be converted to solving a system of differential equations. As an example, a solution of a set of simultaneous algebraic equations by system of differential equations is dealt with in the paper. The solution of a set of algebraic equations by differential equations represents a parallel computation when special units so called integrators are used. All the integrators are working in parallel, e.g. all integrators are controlled by the same algorithm of a numerical integration method. That is why, a parallel interpretation of integrators in a suitable hardware can be expected. We outline the design and implementation of an FPGAbased numerical integrator that will form the basis of our<br>FPGA-based parallel hardware. A

  • Czech name

    Taylor Series Numerical Integrator

  • Czech description

    Simulační jazyk TKSL a Moderní metoda Taylorovy řady mohou být velmi silné nástroje pro extrémně přesné, stabilní a rychlé numerické řešení diferenciálních rovnic. V tomto řešení je možné najít paralelní větve, které mohou být prováděny zároveň. Tyto výpočty provádí prvky, které se označují jako integrátory. Všechny integrátory provádí stejný výpočet jen s jinými daty. Tento postup proto může být jednoduše implementován do hardware. Návrh hardwarového integrátoru je v tomto článku také představen, konkrétně je využito hradlové pole FPGA.<br>

Classification

  • Type

    D - Article in proceedings

  • CEP classification

    JC - Computer hardware and software

  • OECD FORD branch

Result continuities

  • Project

  • Continuities

    Z - Vyzkumny zamer (s odkazem do CEZ)

Others

  • Publication year

    2008

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Article name in the collection

    Second UKSIM European Symposium on Computer Modeling and Simulation

  • ISBN

    978-0-7695-3325-4

  • ISSN

  • e-ISSN

  • Number of pages

    4

  • Pages from-to

  • Publisher name

    IEEE Computer Society

  • Place of publication

    Liverpool

  • Event location

    Liverpool

  • Event date

    Sep 8, 2008

  • Type of event by nationality

    WRD - Celosvětová akce

  • UT code for WoS article