Hardware Accelerator for Evolutionary Image Filters Design
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F09%3APR24513" target="_blank" >RIV/00216305:26230/09:PR24513 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Hardware Accelerator for Evolutionary Image Filters Design
Original language description
The EHWFILTER accelerator was developed in order to accelerate image filter evolution in hardware. It can automatically create a filter (e.g., to suppress shot noise) when noised image and uncorrupted original image are provided. The accelerator is implemented on the COMBO6X card equipped with Virtex II Pro 2VP50ff1517 FPGA. It consists of genetic unit, fitness unit and the so-called virtual reconfigurable circuit (VRC) which is utilized to evaluate candidate filters. Every image filter is considered as a digital circuit of nine 8-bit inputs and a single 8-bit output, which processes grayscale (8-bits/pixel) images. Training images are stored in external SRAM memories. The search algorithm is based on Cartesian Genetic Programming operating over 4x8 programmable elements, population size of 8 individuals, and 1 mutation/chromosome. This setting is default but can be changed. The accelerator is connected with PC using PCI bus. The system requires approx. 10 sec to produce a fi
Czech name
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Czech description
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Classification
Type
G<sub>funk</sub> - Functional sample
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
<a href="/en/project/GA102%2F07%2F0850" target="_blank" >GA102/07/0850: Design and hardware implementation of a patent-invention machine</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2009
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Internal product ID
EHWFILTER
Numerical identification
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Technical parameters
Akcelerátor je implementován na kartě COMBO6X vybavené FPGA Virtex II Pro 2VP50ff1517 obsahující procesor PowerPC. Interně procesor pracuje na 300 MHz, podpůrná logika na 150 MHz. Ostatní komponenty akcelerátoru (virtuální rekonfigurovateln
Economical parameters
Cena závisí na počtu odebíraných kusů.
Application category by cost
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Owner IČO
00216305
Owner name
Vysoké učení technické v Brně
Owner country
CZ - CZECH REPUBLIC
Usage type
N - Využití výsledku jiným subjektem je možné bez nabytí licence (výsledek není licencován)
Licence fee requirement
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Web page
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