Hardware Accelerators for Cartesian Genetic Programming

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F08%3APU76690" target="_blank" >RIV/00216305:26230/08:PU76690 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Hardware Accelerators for Cartesian Genetic Programming
Original language description
A new class of FPGA-based accelerators is presented for Cartesian Genetic Programming (CGP).  The accelerators contain a genetic engine which is reused in all applications. <br>Candidate programs (circuits) are evaluated using application-specific virtual reconfigurable circuit (VRC) and fitness unit. Two types of VRCs are proposed. The first one is devoted for symbolic regression problems over the fixed point representation. The second one is designed for evolution of logic circuits. In bothcases a significant speedup of evolution (30-40 times) was obtained in comparison with a highly optimized software implementation of CGP. This speedup can be increased by creating multiple fitness units.<br>
Czech name
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Czech description
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Project
<a href="/en/project/GA102%2F07%2F0850" target="_blank" >GA102/07/0850: Design and hardware implementation of a patent-invention machine</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year
2008
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Eleventh European Conference on Genetic Programming
ISBN
978-3-540-78670-2
ISSN
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e-ISSN
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Number of pages
12
Pages from-to
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Publisher name
Springer Verlag
Place of publication
Berlin
Event location
Neapol
Event date
Mar 26, 2008
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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