Efficient Hardware Accelerator for Symbolic Regression Problems
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F09%3APU86222" target="_blank" >RIV/00216305:26230/09:PU86222 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Efficient Hardware Accelerator for Symbolic Regression Problems
Original language description
In this paper, a new hardware architecture for the acceleration of symbolic regression problems using Cartesian Genetic Programming (CGP) is presented. <br>In order to minimize the number of expensive memory accesses, a new algorithm is proposed.<br>Thesearch algorithm is implemented using PowerPC processor which is available in Xilinx FPGAs of Virtex family. <br>A significant speedup of evolution is obtained in comparison with a highly optimized software implementation of CGP. <br>
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2009
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
5th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science
ISBN
978-80-87342-04-6
ISSN
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e-ISSN
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Number of pages
8
Pages from-to
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Publisher name
Masaryk University
Place of publication
Znojmo
Event location
Znojmo
Event date
Nov 13, 2009
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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