Packet Header Analysis and Field Extraction for Multigigabit Networks

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F09%3APU82602" target="_blank" >RIV/00216305:26230/09:PU82602 - isvavai.cz</a>
Alternative codes found
RIV/63839172:_____/09:00006565
Result on the web
—
DOI - Digital Object Identifier
—

Result language
angličtina
Original language name
Packet Header Analysis and Field Extraction for Multigigabit Networks
Original language description
Packet header analysis and extraction of header fields needs to be performed in all network devices. As network speed is increasing quickly, high speed packet header processing is required. We propose a new architecture of packet header analysis and fields extraction intended for high-speed FPGA-based network applications. The architecture is able to process 20 Gbps network links with less than 12 percent of available resources of Virtex 5 110 FPGA. Moreover, the presented solution can balance between network throughput and consumed hardware resources to fit application needs. The architecture for packet header processing is generated from standard XML protocol scheme and is strongly optimised for resource consumption and speed by an automatic HDL code  generator. Our solution also enables to change the set of extracted header fields on-line without FPGA reconfiguration.
Czech name
—
Czech description
—

Publication year
2009
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of the 2009 IEEE Symphosium on Design and Diagnostics of Electronic Circuits and Systems
ISBN
978-1-4244-3339-1
ISSN
—
e-ISSN
—
Number of pages
277
Pages from-to
—
Publisher name
IEEE Computer Society
Place of publication
Liberec
Event location
Liberec
Event date
Apr 15, 2009
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
—

Similar results(10)