Packet Classification with Limited Memory Resources
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F17%3APU126458" target="_blank" >RIV/00216305:26230/17:PU126458 - isvavai.cz</a>
Result on the web
<a href="http://dx.doi.org/10.1109/DSD.2017.61" target="_blank" >http://dx.doi.org/10.1109/DSD.2017.61</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/DSD.2017.61" target="_blank" >10.1109/DSD.2017.61</a>
Alternative languages
Result language
angličtina
Original language name
Packet Classification with Limited Memory Resources
Original language description
Network security and monitoring devices use packet classification to match packet header fields in a set of rules. Many hardware architectures have been designed to accelerate packet classification and achieve wire-speed throughput for 100Gbps networks. The architectures are designed for high throughput even for the shortest packets. However, FPGA SoC and Intel Xeon with FPGA have limited resources for multiple accelerators. Usually, it is necessary to balance between available resources and the level of acceleration. Therefore, we have designed new hardware architecture for packet classification, which can balance between the processing speed and hardware resources. To achieve 10 Gbps average throughput the architecture need only 20 BlockRAMs for 5500 rules. Moreover, the architecture can scale the processing speed to wire-speed throughput on 100 Gbps line at the cost of additional memory resources.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
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OECD FORD branch
10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)
Result continuities
Project
<a href="/en/project/VI20152019001" target="_blank" >VI20152019001: Smart Application Aware Embedded Probes</a><br>
Continuities
S - Specificky vyzkum na vysokych skolach
Others
Publication year
2017
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
In proceedings 2017 Euromicro Conference on Digital System Design
ISBN
978-1-5386-2145-5
ISSN
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e-ISSN
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Number of pages
5
Pages from-to
179-183
Publisher name
Institute of Electrical and Electronics Engineers
Place of publication
Vieden
Event location
Vídeň
Event date
Aug 30, 2017
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000427097100024