Hardware Architecture for Packet Classification with Prefix Coloring

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F11%3APU96017" target="_blank" >RIV/00216305:26230/11:PU96017 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Hardware Architecture for Packet Classification with Prefix Coloring
Original language description
Packet classification is a widely used operation in network security devices. As network speeds are increasing, the demand for hardware acceleration of packet classification in FPGAs or ASICs is growing. Nowadays algorithms implemented in hardware can achieve multigigabit speeds, but suffer with great memory overhead. We propose a new algorithm and hardware architecture which reduces memory requirements of decomposition based methods for packet classification. The algorithm uses prefix coloring to reduce large amount of Cartesian product rules at the cost of an additional pipelined processing and a few bits added into results of the longest prefix match operation. The proposed hardware architecture is designed as a processing pipeline with the throughput of 266 million packets per second using commodity FPGA and one external memory. The greatest strength of the algorithm is the constant time complexity of the search operation, which makes the solution resistant to various classes of ne
Czech name
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Czech description
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Publication year
2011
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011
ISBN
978-1-4244-9753-9
ISSN
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e-ISSN
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Number of pages
6
Pages from-to
231-236
Publisher name
IEEE Computer Society
Place of publication
Cottbus
Event location
Cottbus
Event date
Apr 13, 2011
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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