Memory Optimization for Packet Classification Algorithms in FPGA

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F63839172%3A_____%2F10%3A00006835" target="_blank" >RIV/63839172:_____/10:00006835 - isvavai.cz</a>
Alternative codes found
RIV/00216305:26230/10:PU89522
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Memory Optimization for Packet Classification Algorithms in FPGA
Original language description
Packet classification algorithms are widely used in network security devices. As network speeds are increasing, the demand for hardware acceleration of packet classification in FPGAs or ASICs is growing. Nowadays hardware architectures can achieve multigigabit speeds only at the cost of large data structures, which can not fit into the on-chip memory. We propose novel method how to reduce data structure size for the family of decomposition architectures at the cost of additional pipelined processing with only small amount of logic resources. The reduction significantly decreases overhead given by the Cartesian product nature of classification rules. Therefore the data structure can be compressed to 10 % on average. As high compression ratio is achieved, fast on-chip memory can be used to store data structures and hardware architectures can process network traffic at significantly higher speed.
Czech name
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Czech description
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Publication year
2010
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems
ISBN
978-1-4244-6610-8
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
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Publisher name
IEEE Computer Society
Place of publication
Vídeň
Event location
Vídeň
Event date
Jan 1, 2010
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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