Cycle Accurate Profiler for ASIPs
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F09%3APU86224" target="_blank" >RIV/00216305:26230/09:PU86224 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Cycle Accurate Profiler for ASIPs
Original language description
The simulation of one processor on another is an important part of processor development because simulation is the way in witch a designer can verify and validate processor's instruction set, its micro-architecture or program, which will be executed on this processor. But a simple simulation is not sufficient in cases where the developer wants to optimize an executed program or processor's parts. For this purpose a profiler is used. The profiler is a tool tracing processor activities, so it provides theinformation about utilization of particular parts. In this paper a technique creating a profiler from a processor description in an architecture description language is proposed.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2009
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
5th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science
ISBN
978-80-87342-04-6
ISSN
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e-ISSN
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Number of pages
8
Pages from-to
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Publisher name
Masaryk University
Place of publication
Brno
Event location
Znojmo
Event date
Nov 13, 2009
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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