Fast Cycle-Accurate Interpreted Simulation

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F09%3APU86259" target="_blank" >RIV/00216305:26230/09:PU86259 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Fast Cycle-Accurate Interpreted Simulation
Original language description
 <p> The area of hardware/software co-design deals with the design of ASIPs(Application Specific Instruction-set Processors) because they often create the core of an embedded system. Embedded systems with ASIPs are designed for a given task and they have to fulfill several criteria, such as power consumption, chip size, etc. The success of the design phase is closely related to the existence of good design tools, i.e. tools for ASIP programming and simulation. The simulation itself is very important, because with it we can verify and validate an ASIP design. For this purpose, ASIPs are described using an architecture description language that allows generating the design tools in an automatic way. In this article, we focus on presenting the principles which are used in our fast cycle-accurate interpreted simulator. Beside the simulation speed, we also focus on equivalence assurance between an ASIP simulator and its hard
Czech name
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Czech description
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Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year
2009
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Tenth International Workshop on Microprocessor Test and Verification: Common Challenges and Solutions
ISBN
978-0-7695-4000-9
ISSN
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e-ISSN
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Number of pages
6
Pages from-to
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Publisher name
IEEE Computer Society Press
Place of publication
Austin
Event location
Austin, Texas
Event date
Dec 7, 2009
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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