Hardware Accelerated Pattern Matching Based on Deterministic Finite Automata with Perfect Hashing
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F10%3APU89524" target="_blank" >RIV/00216305:26230/10:PU89524 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Hardware Accelerated Pattern Matching Based on Deterministic Finite Automata with Perfect Hashing
Original language description
With the increased amount of data transferred by<br>computer networks, the amount of the malicious traffic also<br>increases and therefore it is necessary to protect networks<br>by security systems such as firewalls and Intrusion Detection<br>Systems (IDS) operating at multigigabit speeds. Pattern matching<br>is the time critical operation of current IDS. This paper deals<br>with the analysis of regular expressions used by modern IDS<br>to describe malicious traffic. According to our analysis, more<br>than 64 percent of regular expressions create Deterministic Finite<br>Automaton (DFA) with less than 20 percent of saturation of<br>the transition table which allows efficient implementation of<br>pattern matching into FPGA platform. We propose architecture<br>for fast pattern matching using perfect hashing suitable for<br>implementation into FPGA platform. The memory requirements<br>of presented architecture is closed to the theoretical minimum<br>for sparse transition tables.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
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Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)<br>S - Specificky vyzkum na vysokych skolach
Others
Publication year
2010
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS 2010
ISBN
978-1-4244-6610-8
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
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Publisher name
IEEE Computer Society
Place of publication
Vienna
Event location
Vienna
Event date
Apr 14, 2010
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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