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High level validation of an optimization algorithm for the implementation of adaptive Wavelet Transforms in FPGAs

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F10%3APU89605" target="_blank" >RIV/00216305:26230/10:PU89605 - isvavai.cz</a>

  • Result on the web

  • DOI - Digital Object Identifier

Alternative languages

  • Result language

    angličtina

  • Original language name

    High level validation of an optimization algorithm for the implementation of adaptive Wavelet Transforms in FPGAs

  • Original language description

    The work reported in this paper describes the steps given towards an FPGA-based implementation of evolvable wavelet transforms for image compression in embedded systems. An Evolutionary Algorithm (EA) for the design and optimization of the transform coefficients is tailored for a suitable System on Chip implementation. Several cut downs on the computing requirements have been done to the original algorithm, adapting it for the FPGA implementation. What this paper addresses more specifically is the validation of the algorithm using fixed point arithmetic for the whole optimization process. The results show how high quality transforms are evolved from scratch with limited precision arithmetic. Also, preliminary results of the implementation in an FPGA device are included.

  • Czech name

  • Czech description

Classification

  • Type

    D - Article in proceedings

  • CEP classification

    IN - Informatics

  • OECD FORD branch

Result continuities

  • Project

    <a href="/en/project/GAP103%2F10%2F1517" target="_blank" >GAP103/10/1517: Natural Computing on Unconventional Platforms</a><br>

  • Continuities

    Z - Vyzkumny zamer (s odkazem do CEZ)

Others

  • Publication year

    2010

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Article name in the collection

    Proc. of 13th Euromicro Conference on Digital System Design

  • ISBN

    978-0-7695-4171-6

  • ISSN

  • e-ISSN

  • Number of pages

    8

  • Pages from-to

    96-103

  • Publisher name

    IEEE Computer Society

  • Place of publication

    Los Alamitos

  • Event location

    Lille

  • Event date

    Sep 1, 2010

  • Type of event by nationality

    WRD - Celosvětová akce

  • UT code for WoS article